1. Field of the Invention
The present invention relates to a method of refreshing memory cells within a dynamic random access memory (DRAM), and in particular, to a method which reduces the refresh noise on the drain voltage of a DRAM using CMOS.
2. Description of the Related Art
As is well known in the art, dynamic random access memories require periodic refreshing of the memory cells within the DRAM so that the data stored within each memory cell does not corrupt or decay over time. By periodically refreshing each row of memory within a DRAM, energy is supplied to each of the capacitive memory cells within the row so that the data stored in the memory cells does not decay. Thus, refreshing is an essential element of memory storage for volatile memories.
A refresh may be a CAS (column address select) before RAS (row address select) refresh, or a RAS-only refresh. A CAS before RAS refresh involves asserting the CAS signal before the RAS signal is asserted to indicate that the next cycle is a refresh cycle. In response to the assertion of a CAS before a RAS, an internal address counter in the memory supplies the row address of the next row to be refreshed. A RAS-only refresh operates in a similar manner to refresh selected rows of memory; however, the address of the row to be refreshed is instead supplied by an external refresh circuit.
Whenever a refresh is performed, however, a current surge in the refreshed DRAM results in a drop of the line voltage supplying the DRAM. The noise caused by the drop in line voltage can affect the operation of that DRAM or other DRAMs supplied by the same voltage. This is particularly true in DRAMs which employ CMOS technology, since the internal circuitry of such DRAMS is particularly susceptible to sudden voltage drops or noise.
Thus, in order to prevent large noise spikes during a refresh cycle, previous refresh methods have contemplated staggering refreshes applied to adjacent single in-line memory modules (SIMMs) so that the refreshes occur one after the other and are separated by at least one clock cycle. Furthermore, in order to reduce the amount of voltage drop caused by refresh accesses, filtering capacitors are provided for each memory bank to hold the line voltage up during a high current draw. Although this approach serves to distribute the voltage drop produced during a refresh evenly over multiple clock cycles, voltage drop reduction is still not optimized. This is because sometimes adjacent memory banks share one or more filtering capacitors so that if, for example, the first and second memory banks are refreshed in sequence, the filtering capacitors do not have sufficient recovery time to recharge to the nominal line voltage. Thus, if memory banks sharing the same filtering capacitor are refreshed in consecutive clock cycles, there is a possibility that a significant voltage drop will be observed on the voltage supply line connected to the accessed memory banks and that the resulting noise will affect the operation of the DRAMs.